;
; File Name: cyfitteriar.inc
; 
; PSoC Creator  4.2
;
; Description:
; 
;
;-------------------------------------------------------------------------------
; Copyright (c) 2007-2018 Cypress Semiconductor.  All rights reserved.
; You may use this file only in accordance with the license, terms, conditions, 
; disclaimers, and limitations in the end user license agreement accompanying 
; the software package with which this file was provided.
;-------------------------------------------------------------------------------

#ifndef INCLUDED_CYFITTERIAR_INC
#define INCLUDED_CYFITTERIAR_INC
    INCLUDE cydeviceiar_trm.inc

/* SW1 */
SW1__0__DM__MASK EQU 0xE00000
SW1__0__DM__SHIFT EQU 21
SW1__0__DR EQU CYREG_PRT0_DR
SW1__0__HSIOM EQU CYREG_HSIOM_PORT_SEL0
SW1__0__HSIOM_MASK EQU 0xF0000000
SW1__0__HSIOM_SHIFT EQU 28
SW1__0__INTCFG EQU CYREG_PRT0_INTCFG
SW1__0__INTSTAT EQU CYREG_PRT0_INTSTAT
SW1__0__MASK EQU 0x80
SW1__0__PA__CFG0 EQU CYREG_UDB_PA0_CFG0
SW1__0__PA__CFG1 EQU CYREG_UDB_PA0_CFG1
SW1__0__PA__CFG10 EQU CYREG_UDB_PA0_CFG10
SW1__0__PA__CFG11 EQU CYREG_UDB_PA0_CFG11
SW1__0__PA__CFG12 EQU CYREG_UDB_PA0_CFG12
SW1__0__PA__CFG13 EQU CYREG_UDB_PA0_CFG13
SW1__0__PA__CFG14 EQU CYREG_UDB_PA0_CFG14
SW1__0__PA__CFG2 EQU CYREG_UDB_PA0_CFG2
SW1__0__PA__CFG3 EQU CYREG_UDB_PA0_CFG3
SW1__0__PA__CFG4 EQU CYREG_UDB_PA0_CFG4
SW1__0__PA__CFG5 EQU CYREG_UDB_PA0_CFG5
SW1__0__PA__CFG6 EQU CYREG_UDB_PA0_CFG6
SW1__0__PA__CFG7 EQU CYREG_UDB_PA0_CFG7
SW1__0__PA__CFG8 EQU CYREG_UDB_PA0_CFG8
SW1__0__PA__CFG9 EQU CYREG_UDB_PA0_CFG9
SW1__0__PC EQU CYREG_PRT0_PC
SW1__0__PC2 EQU CYREG_PRT0_PC2
SW1__0__PORT EQU 0
SW1__0__PS EQU CYREG_PRT0_PS
SW1__0__SHIFT EQU 7
SW1__DR EQU CYREG_PRT0_DR
SW1__INTCFG EQU CYREG_PRT0_INTCFG
SW1__INTSTAT EQU CYREG_PRT0_INTSTAT
SW1__MASK EQU 0x80
SW1__PA__CFG0 EQU CYREG_UDB_PA0_CFG0
SW1__PA__CFG1 EQU CYREG_UDB_PA0_CFG1
SW1__PA__CFG10 EQU CYREG_UDB_PA0_CFG10
SW1__PA__CFG11 EQU CYREG_UDB_PA0_CFG11
SW1__PA__CFG12 EQU CYREG_UDB_PA0_CFG12
SW1__PA__CFG13 EQU CYREG_UDB_PA0_CFG13
SW1__PA__CFG14 EQU CYREG_UDB_PA0_CFG14
SW1__PA__CFG2 EQU CYREG_UDB_PA0_CFG2
SW1__PA__CFG3 EQU CYREG_UDB_PA0_CFG3
SW1__PA__CFG4 EQU CYREG_UDB_PA0_CFG4
SW1__PA__CFG5 EQU CYREG_UDB_PA0_CFG5
SW1__PA__CFG6 EQU CYREG_UDB_PA0_CFG6
SW1__PA__CFG7 EQU CYREG_UDB_PA0_CFG7
SW1__PA__CFG8 EQU CYREG_UDB_PA0_CFG8
SW1__PA__CFG9 EQU CYREG_UDB_PA0_CFG9
SW1__PC EQU CYREG_PRT0_PC
SW1__PC2 EQU CYREG_PRT0_PC2
SW1__PORT EQU 0
SW1__PS EQU CYREG_PRT0_PS
SW1__SHIFT EQU 7

/* SW2 */
SW2__0__DM__MASK EQU 0x07
SW2__0__DM__SHIFT EQU 0
SW2__0__DR EQU CYREG_PRT0_DR
SW2__0__HSIOM EQU CYREG_HSIOM_PORT_SEL0
SW2__0__HSIOM_MASK EQU 0x0000000F
SW2__0__HSIOM_SHIFT EQU 0
SW2__0__INTCFG EQU CYREG_PRT0_INTCFG
SW2__0__INTSTAT EQU CYREG_PRT0_INTSTAT
SW2__0__MASK EQU 0x01
SW2__0__PA__CFG0 EQU CYREG_UDB_PA0_CFG0
SW2__0__PA__CFG1 EQU CYREG_UDB_PA0_CFG1
SW2__0__PA__CFG10 EQU CYREG_UDB_PA0_CFG10
SW2__0__PA__CFG11 EQU CYREG_UDB_PA0_CFG11
SW2__0__PA__CFG12 EQU CYREG_UDB_PA0_CFG12
SW2__0__PA__CFG13 EQU CYREG_UDB_PA0_CFG13
SW2__0__PA__CFG14 EQU CYREG_UDB_PA0_CFG14
SW2__0__PA__CFG2 EQU CYREG_UDB_PA0_CFG2
SW2__0__PA__CFG3 EQU CYREG_UDB_PA0_CFG3
SW2__0__PA__CFG4 EQU CYREG_UDB_PA0_CFG4
SW2__0__PA__CFG5 EQU CYREG_UDB_PA0_CFG5
SW2__0__PA__CFG6 EQU CYREG_UDB_PA0_CFG6
SW2__0__PA__CFG7 EQU CYREG_UDB_PA0_CFG7
SW2__0__PA__CFG8 EQU CYREG_UDB_PA0_CFG8
SW2__0__PA__CFG9 EQU CYREG_UDB_PA0_CFG9
SW2__0__PC EQU CYREG_PRT0_PC
SW2__0__PC2 EQU CYREG_PRT0_PC2
SW2__0__PORT EQU 0
SW2__0__PS EQU CYREG_PRT0_PS
SW2__0__SHIFT EQU 0
SW2__DR EQU CYREG_PRT0_DR
SW2__INTCFG EQU CYREG_PRT0_INTCFG
SW2__INTSTAT EQU CYREG_PRT0_INTSTAT
SW2__MASK EQU 0x01
SW2__PA__CFG0 EQU CYREG_UDB_PA0_CFG0
SW2__PA__CFG1 EQU CYREG_UDB_PA0_CFG1
SW2__PA__CFG10 EQU CYREG_UDB_PA0_CFG10
SW2__PA__CFG11 EQU CYREG_UDB_PA0_CFG11
SW2__PA__CFG12 EQU CYREG_UDB_PA0_CFG12
SW2__PA__CFG13 EQU CYREG_UDB_PA0_CFG13
SW2__PA__CFG14 EQU CYREG_UDB_PA0_CFG14
SW2__PA__CFG2 EQU CYREG_UDB_PA0_CFG2
SW2__PA__CFG3 EQU CYREG_UDB_PA0_CFG3
SW2__PA__CFG4 EQU CYREG_UDB_PA0_CFG4
SW2__PA__CFG5 EQU CYREG_UDB_PA0_CFG5
SW2__PA__CFG6 EQU CYREG_UDB_PA0_CFG6
SW2__PA__CFG7 EQU CYREG_UDB_PA0_CFG7
SW2__PA__CFG8 EQU CYREG_UDB_PA0_CFG8
SW2__PA__CFG9 EQU CYREG_UDB_PA0_CFG9
SW2__PC EQU CYREG_PRT0_PC
SW2__PC2 EQU CYREG_PRT0_PC2
SW2__PORT EQU 0
SW2__PS EQU CYREG_PRT0_PS
SW2__SHIFT EQU 0

/* SW3 */
SW3__0__DM__MASK EQU 0x38000
SW3__0__DM__SHIFT EQU 15
SW3__0__DR EQU CYREG_PRT3_DR
SW3__0__HSIOM EQU CYREG_HSIOM_PORT_SEL3
SW3__0__HSIOM_MASK EQU 0x00F00000
SW3__0__HSIOM_SHIFT EQU 20
SW3__0__INTCFG EQU CYREG_PRT3_INTCFG
SW3__0__INTSTAT EQU CYREG_PRT3_INTSTAT
SW3__0__MASK EQU 0x20
SW3__0__PA__CFG0 EQU CYREG_UDB_PA3_CFG0
SW3__0__PA__CFG1 EQU CYREG_UDB_PA3_CFG1
SW3__0__PA__CFG10 EQU CYREG_UDB_PA3_CFG10
SW3__0__PA__CFG11 EQU CYREG_UDB_PA3_CFG11
SW3__0__PA__CFG12 EQU CYREG_UDB_PA3_CFG12
SW3__0__PA__CFG13 EQU CYREG_UDB_PA3_CFG13
SW3__0__PA__CFG14 EQU CYREG_UDB_PA3_CFG14
SW3__0__PA__CFG2 EQU CYREG_UDB_PA3_CFG2
SW3__0__PA__CFG3 EQU CYREG_UDB_PA3_CFG3
SW3__0__PA__CFG4 EQU CYREG_UDB_PA3_CFG4
SW3__0__PA__CFG5 EQU CYREG_UDB_PA3_CFG5
SW3__0__PA__CFG6 EQU CYREG_UDB_PA3_CFG6
SW3__0__PA__CFG7 EQU CYREG_UDB_PA3_CFG7
SW3__0__PA__CFG8 EQU CYREG_UDB_PA3_CFG8
SW3__0__PA__CFG9 EQU CYREG_UDB_PA3_CFG9
SW3__0__PC EQU CYREG_PRT3_PC
SW3__0__PC2 EQU CYREG_PRT3_PC2
SW3__0__PORT EQU 3
SW3__0__PS EQU CYREG_PRT3_PS
SW3__0__SHIFT EQU 5
SW3__DR EQU CYREG_PRT3_DR
SW3__INTCFG EQU CYREG_PRT3_INTCFG
SW3__INTSTAT EQU CYREG_PRT3_INTSTAT
SW3__MASK EQU 0x20
SW3__PA__CFG0 EQU CYREG_UDB_PA3_CFG0
SW3__PA__CFG1 EQU CYREG_UDB_PA3_CFG1
SW3__PA__CFG10 EQU CYREG_UDB_PA3_CFG10
SW3__PA__CFG11 EQU CYREG_UDB_PA3_CFG11
SW3__PA__CFG12 EQU CYREG_UDB_PA3_CFG12
SW3__PA__CFG13 EQU CYREG_UDB_PA3_CFG13
SW3__PA__CFG14 EQU CYREG_UDB_PA3_CFG14
SW3__PA__CFG2 EQU CYREG_UDB_PA3_CFG2
SW3__PA__CFG3 EQU CYREG_UDB_PA3_CFG3
SW3__PA__CFG4 EQU CYREG_UDB_PA3_CFG4
SW3__PA__CFG5 EQU CYREG_UDB_PA3_CFG5
SW3__PA__CFG6 EQU CYREG_UDB_PA3_CFG6
SW3__PA__CFG7 EQU CYREG_UDB_PA3_CFG7
SW3__PA__CFG8 EQU CYREG_UDB_PA3_CFG8
SW3__PA__CFG9 EQU CYREG_UDB_PA3_CFG9
SW3__PC EQU CYREG_PRT3_PC
SW3__PC2 EQU CYREG_PRT3_PC2
SW3__PORT EQU 3
SW3__PS EQU CYREG_PRT3_PS
SW3__SHIFT EQU 5

/* NSLP */
NSLP__0__DM__MASK EQU 0x1C0
NSLP__0__DM__SHIFT EQU 6
NSLP__0__DR EQU CYREG_PRT2_DR
NSLP__0__HSIOM EQU CYREG_HSIOM_PORT_SEL2
NSLP__0__HSIOM_MASK EQU 0x00000F00
NSLP__0__HSIOM_SHIFT EQU 8
NSLP__0__INTCFG EQU CYREG_PRT2_INTCFG
NSLP__0__INTSTAT EQU CYREG_PRT2_INTSTAT
NSLP__0__MASK EQU 0x04
NSLP__0__PA__CFG0 EQU CYREG_UDB_PA2_CFG0
NSLP__0__PA__CFG1 EQU CYREG_UDB_PA2_CFG1
NSLP__0__PA__CFG10 EQU CYREG_UDB_PA2_CFG10
NSLP__0__PA__CFG11 EQU CYREG_UDB_PA2_CFG11
NSLP__0__PA__CFG12 EQU CYREG_UDB_PA2_CFG12
NSLP__0__PA__CFG13 EQU CYREG_UDB_PA2_CFG13
NSLP__0__PA__CFG14 EQU CYREG_UDB_PA2_CFG14
NSLP__0__PA__CFG2 EQU CYREG_UDB_PA2_CFG2
NSLP__0__PA__CFG3 EQU CYREG_UDB_PA2_CFG3
NSLP__0__PA__CFG4 EQU CYREG_UDB_PA2_CFG4
NSLP__0__PA__CFG5 EQU CYREG_UDB_PA2_CFG5
NSLP__0__PA__CFG6 EQU CYREG_UDB_PA2_CFG6
NSLP__0__PA__CFG7 EQU CYREG_UDB_PA2_CFG7
NSLP__0__PA__CFG8 EQU CYREG_UDB_PA2_CFG8
NSLP__0__PA__CFG9 EQU CYREG_UDB_PA2_CFG9
NSLP__0__PC EQU CYREG_PRT2_PC
NSLP__0__PC2 EQU CYREG_PRT2_PC2
NSLP__0__PORT EQU 2
NSLP__0__PS EQU CYREG_PRT2_PS
NSLP__0__SHIFT EQU 2
NSLP__DR EQU CYREG_PRT2_DR
NSLP__INTCFG EQU CYREG_PRT2_INTCFG
NSLP__INTSTAT EQU CYREG_PRT2_INTSTAT
NSLP__MASK EQU 0x04
NSLP__PA__CFG0 EQU CYREG_UDB_PA2_CFG0
NSLP__PA__CFG1 EQU CYREG_UDB_PA2_CFG1
NSLP__PA__CFG10 EQU CYREG_UDB_PA2_CFG10
NSLP__PA__CFG11 EQU CYREG_UDB_PA2_CFG11
NSLP__PA__CFG12 EQU CYREG_UDB_PA2_CFG12
NSLP__PA__CFG13 EQU CYREG_UDB_PA2_CFG13
NSLP__PA__CFG14 EQU CYREG_UDB_PA2_CFG14
NSLP__PA__CFG2 EQU CYREG_UDB_PA2_CFG2
NSLP__PA__CFG3 EQU CYREG_UDB_PA2_CFG3
NSLP__PA__CFG4 EQU CYREG_UDB_PA2_CFG4
NSLP__PA__CFG5 EQU CYREG_UDB_PA2_CFG5
NSLP__PA__CFG6 EQU CYREG_UDB_PA2_CFG6
NSLP__PA__CFG7 EQU CYREG_UDB_PA2_CFG7
NSLP__PA__CFG8 EQU CYREG_UDB_PA2_CFG8
NSLP__PA__CFG9 EQU CYREG_UDB_PA2_CFG9
NSLP__PC EQU CYREG_PRT2_PC
NSLP__PC2 EQU CYREG_PRT2_PC2
NSLP__PORT EQU 2
NSLP__PS EQU CYREG_PRT2_PS
NSLP__SHIFT EQU 2

/* LED_RED */
LED_RED__0__DM__MASK EQU 0x1C0000
LED_RED__0__DM__SHIFT EQU 18
LED_RED__0__DR EQU CYREG_PRT1_DR
LED_RED__0__HSIOM EQU CYREG_HSIOM_PORT_SEL1
LED_RED__0__HSIOM_MASK EQU 0x0F000000
LED_RED__0__HSIOM_SHIFT EQU 24
LED_RED__0__INTCFG EQU CYREG_PRT1_INTCFG
LED_RED__0__INTSTAT EQU CYREG_PRT1_INTSTAT
LED_RED__0__MASK EQU 0x40
LED_RED__0__PA__CFG0 EQU CYREG_UDB_PA1_CFG0
LED_RED__0__PA__CFG1 EQU CYREG_UDB_PA1_CFG1
LED_RED__0__PA__CFG10 EQU CYREG_UDB_PA1_CFG10
LED_RED__0__PA__CFG11 EQU CYREG_UDB_PA1_CFG11
LED_RED__0__PA__CFG12 EQU CYREG_UDB_PA1_CFG12
LED_RED__0__PA__CFG13 EQU CYREG_UDB_PA1_CFG13
LED_RED__0__PA__CFG14 EQU CYREG_UDB_PA1_CFG14
LED_RED__0__PA__CFG2 EQU CYREG_UDB_PA1_CFG2
LED_RED__0__PA__CFG3 EQU CYREG_UDB_PA1_CFG3
LED_RED__0__PA__CFG4 EQU CYREG_UDB_PA1_CFG4
LED_RED__0__PA__CFG5 EQU CYREG_UDB_PA1_CFG5
LED_RED__0__PA__CFG6 EQU CYREG_UDB_PA1_CFG6
LED_RED__0__PA__CFG7 EQU CYREG_UDB_PA1_CFG7
LED_RED__0__PA__CFG8 EQU CYREG_UDB_PA1_CFG8
LED_RED__0__PA__CFG9 EQU CYREG_UDB_PA1_CFG9
LED_RED__0__PC EQU CYREG_PRT1_PC
LED_RED__0__PC2 EQU CYREG_PRT1_PC2
LED_RED__0__PORT EQU 1
LED_RED__0__PS EQU CYREG_PRT1_PS
LED_RED__0__SHIFT EQU 6
LED_RED__DR EQU CYREG_PRT1_DR
LED_RED__INTCFG EQU CYREG_PRT1_INTCFG
LED_RED__INTSTAT EQU CYREG_PRT1_INTSTAT
LED_RED__MASK EQU 0x40
LED_RED__PA__CFG0 EQU CYREG_UDB_PA1_CFG0
LED_RED__PA__CFG1 EQU CYREG_UDB_PA1_CFG1
LED_RED__PA__CFG10 EQU CYREG_UDB_PA1_CFG10
LED_RED__PA__CFG11 EQU CYREG_UDB_PA1_CFG11
LED_RED__PA__CFG12 EQU CYREG_UDB_PA1_CFG12
LED_RED__PA__CFG13 EQU CYREG_UDB_PA1_CFG13
LED_RED__PA__CFG14 EQU CYREG_UDB_PA1_CFG14
LED_RED__PA__CFG2 EQU CYREG_UDB_PA1_CFG2
LED_RED__PA__CFG3 EQU CYREG_UDB_PA1_CFG3
LED_RED__PA__CFG4 EQU CYREG_UDB_PA1_CFG4
LED_RED__PA__CFG5 EQU CYREG_UDB_PA1_CFG5
LED_RED__PA__CFG6 EQU CYREG_UDB_PA1_CFG6
LED_RED__PA__CFG7 EQU CYREG_UDB_PA1_CFG7
LED_RED__PA__CFG8 EQU CYREG_UDB_PA1_CFG8
LED_RED__PA__CFG9 EQU CYREG_UDB_PA1_CFG9
LED_RED__PC EQU CYREG_PRT1_PC
LED_RED__PC2 EQU CYREG_PRT1_PC2
LED_RED__PORT EQU 1
LED_RED__PS EQU CYREG_PRT1_PS
LED_RED__SHIFT EQU 6

/* LED_BLUE */
LED_BLUE__0__DM__MASK EQU 0xE00
LED_BLUE__0__DM__SHIFT EQU 9
LED_BLUE__0__DR EQU CYREG_PRT0_DR
LED_BLUE__0__HSIOM EQU CYREG_HSIOM_PORT_SEL0
LED_BLUE__0__HSIOM_MASK EQU 0x0000F000
LED_BLUE__0__HSIOM_SHIFT EQU 12
LED_BLUE__0__INTCFG EQU CYREG_PRT0_INTCFG
LED_BLUE__0__INTSTAT EQU CYREG_PRT0_INTSTAT
LED_BLUE__0__MASK EQU 0x08
LED_BLUE__0__PA__CFG0 EQU CYREG_UDB_PA0_CFG0
LED_BLUE__0__PA__CFG1 EQU CYREG_UDB_PA0_CFG1
LED_BLUE__0__PA__CFG10 EQU CYREG_UDB_PA0_CFG10
LED_BLUE__0__PA__CFG11 EQU CYREG_UDB_PA0_CFG11
LED_BLUE__0__PA__CFG12 EQU CYREG_UDB_PA0_CFG12
LED_BLUE__0__PA__CFG13 EQU CYREG_UDB_PA0_CFG13
LED_BLUE__0__PA__CFG14 EQU CYREG_UDB_PA0_CFG14
LED_BLUE__0__PA__CFG2 EQU CYREG_UDB_PA0_CFG2
LED_BLUE__0__PA__CFG3 EQU CYREG_UDB_PA0_CFG3
LED_BLUE__0__PA__CFG4 EQU CYREG_UDB_PA0_CFG4
LED_BLUE__0__PA__CFG5 EQU CYREG_UDB_PA0_CFG5
LED_BLUE__0__PA__CFG6 EQU CYREG_UDB_PA0_CFG6
LED_BLUE__0__PA__CFG7 EQU CYREG_UDB_PA0_CFG7
LED_BLUE__0__PA__CFG8 EQU CYREG_UDB_PA0_CFG8
LED_BLUE__0__PA__CFG9 EQU CYREG_UDB_PA0_CFG9
LED_BLUE__0__PC EQU CYREG_PRT0_PC
LED_BLUE__0__PC2 EQU CYREG_PRT0_PC2
LED_BLUE__0__PORT EQU 0
LED_BLUE__0__PS EQU CYREG_PRT0_PS
LED_BLUE__0__SHIFT EQU 3
LED_BLUE__DR EQU CYREG_PRT0_DR
LED_BLUE__INTCFG EQU CYREG_PRT0_INTCFG
LED_BLUE__INTSTAT EQU CYREG_PRT0_INTSTAT
LED_BLUE__MASK EQU 0x08
LED_BLUE__PA__CFG0 EQU CYREG_UDB_PA0_CFG0
LED_BLUE__PA__CFG1 EQU CYREG_UDB_PA0_CFG1
LED_BLUE__PA__CFG10 EQU CYREG_UDB_PA0_CFG10
LED_BLUE__PA__CFG11 EQU CYREG_UDB_PA0_CFG11
LED_BLUE__PA__CFG12 EQU CYREG_UDB_PA0_CFG12
LED_BLUE__PA__CFG13 EQU CYREG_UDB_PA0_CFG13
LED_BLUE__PA__CFG14 EQU CYREG_UDB_PA0_CFG14
LED_BLUE__PA__CFG2 EQU CYREG_UDB_PA0_CFG2
LED_BLUE__PA__CFG3 EQU CYREG_UDB_PA0_CFG3
LED_BLUE__PA__CFG4 EQU CYREG_UDB_PA0_CFG4
LED_BLUE__PA__CFG5 EQU CYREG_UDB_PA0_CFG5
LED_BLUE__PA__CFG6 EQU CYREG_UDB_PA0_CFG6
LED_BLUE__PA__CFG7 EQU CYREG_UDB_PA0_CFG7
LED_BLUE__PA__CFG8 EQU CYREG_UDB_PA0_CFG8
LED_BLUE__PA__CFG9 EQU CYREG_UDB_PA0_CFG9
LED_BLUE__PC EQU CYREG_PRT0_PC
LED_BLUE__PC2 EQU CYREG_PRT0_PC2
LED_BLUE__PORT EQU 0
LED_BLUE__PS EQU CYREG_PRT0_PS
LED_BLUE__SHIFT EQU 3

/* LED_GREEN */
LED_GREEN__0__DM__MASK EQU 0x1C0
LED_GREEN__0__DM__SHIFT EQU 6
LED_GREEN__0__DR EQU CYREG_PRT0_DR
LED_GREEN__0__HSIOM EQU CYREG_HSIOM_PORT_SEL0
LED_GREEN__0__HSIOM_MASK EQU 0x00000F00
LED_GREEN__0__HSIOM_SHIFT EQU 8
LED_GREEN__0__INTCFG EQU CYREG_PRT0_INTCFG
LED_GREEN__0__INTSTAT EQU CYREG_PRT0_INTSTAT
LED_GREEN__0__MASK EQU 0x04
LED_GREEN__0__PA__CFG0 EQU CYREG_UDB_PA0_CFG0
LED_GREEN__0__PA__CFG1 EQU CYREG_UDB_PA0_CFG1
LED_GREEN__0__PA__CFG10 EQU CYREG_UDB_PA0_CFG10
LED_GREEN__0__PA__CFG11 EQU CYREG_UDB_PA0_CFG11
LED_GREEN__0__PA__CFG12 EQU CYREG_UDB_PA0_CFG12
LED_GREEN__0__PA__CFG13 EQU CYREG_UDB_PA0_CFG13
LED_GREEN__0__PA__CFG14 EQU CYREG_UDB_PA0_CFG14
LED_GREEN__0__PA__CFG2 EQU CYREG_UDB_PA0_CFG2
LED_GREEN__0__PA__CFG3 EQU CYREG_UDB_PA0_CFG3
LED_GREEN__0__PA__CFG4 EQU CYREG_UDB_PA0_CFG4
LED_GREEN__0__PA__CFG5 EQU CYREG_UDB_PA0_CFG5
LED_GREEN__0__PA__CFG6 EQU CYREG_UDB_PA0_CFG6
LED_GREEN__0__PA__CFG7 EQU CYREG_UDB_PA0_CFG7
LED_GREEN__0__PA__CFG8 EQU CYREG_UDB_PA0_CFG8
LED_GREEN__0__PA__CFG9 EQU CYREG_UDB_PA0_CFG9
LED_GREEN__0__PC EQU CYREG_PRT0_PC
LED_GREEN__0__PC2 EQU CYREG_PRT0_PC2
LED_GREEN__0__PORT EQU 0
LED_GREEN__0__PS EQU CYREG_PRT0_PS
LED_GREEN__0__SHIFT EQU 2
LED_GREEN__DR EQU CYREG_PRT0_DR
LED_GREEN__INTCFG EQU CYREG_PRT0_INTCFG
LED_GREEN__INTSTAT EQU CYREG_PRT0_INTSTAT
LED_GREEN__MASK EQU 0x04
LED_GREEN__PA__CFG0 EQU CYREG_UDB_PA0_CFG0
LED_GREEN__PA__CFG1 EQU CYREG_UDB_PA0_CFG1
LED_GREEN__PA__CFG10 EQU CYREG_UDB_PA0_CFG10
LED_GREEN__PA__CFG11 EQU CYREG_UDB_PA0_CFG11
LED_GREEN__PA__CFG12 EQU CYREG_UDB_PA0_CFG12
LED_GREEN__PA__CFG13 EQU CYREG_UDB_PA0_CFG13
LED_GREEN__PA__CFG14 EQU CYREG_UDB_PA0_CFG14
LED_GREEN__PA__CFG2 EQU CYREG_UDB_PA0_CFG2
LED_GREEN__PA__CFG3 EQU CYREG_UDB_PA0_CFG3
LED_GREEN__PA__CFG4 EQU CYREG_UDB_PA0_CFG4
LED_GREEN__PA__CFG5 EQU CYREG_UDB_PA0_CFG5
LED_GREEN__PA__CFG6 EQU CYREG_UDB_PA0_CFG6
LED_GREEN__PA__CFG7 EQU CYREG_UDB_PA0_CFG7
LED_GREEN__PA__CFG8 EQU CYREG_UDB_PA0_CFG8
LED_GREEN__PA__CFG9 EQU CYREG_UDB_PA0_CFG9
LED_GREEN__PC EQU CYREG_PRT0_PC
LED_GREEN__PC2 EQU CYREG_PRT0_PC2
LED_GREEN__PORT EQU 0
LED_GREEN__PS EQU CYREG_PRT0_PS
LED_GREEN__SHIFT EQU 2

/* UART_MASTER */
UART_MASTER_rx__0__DM__MASK EQU 0x7000
UART_MASTER_rx__0__DM__SHIFT EQU 12
UART_MASTER_rx__0__DR EQU CYREG_PRT0_DR
UART_MASTER_rx__0__HSIOM EQU CYREG_HSIOM_PORT_SEL0
UART_MASTER_rx__0__HSIOM_GPIO EQU 0
UART_MASTER_rx__0__HSIOM_I2C EQU 14
UART_MASTER_rx__0__HSIOM_I2C_SCL EQU 14
UART_MASTER_rx__0__HSIOM_MASK EQU 0x000F0000
UART_MASTER_rx__0__HSIOM_SHIFT EQU 16
UART_MASTER_rx__0__HSIOM_SPI EQU 15
UART_MASTER_rx__0__HSIOM_SPI_MOSI EQU 15
UART_MASTER_rx__0__HSIOM_UART EQU 9
UART_MASTER_rx__0__HSIOM_UART_RX EQU 9
UART_MASTER_rx__0__INTCFG EQU CYREG_PRT0_INTCFG
UART_MASTER_rx__0__INTSTAT EQU CYREG_PRT0_INTSTAT
UART_MASTER_rx__0__MASK EQU 0x10
UART_MASTER_rx__0__PA__CFG0 EQU CYREG_UDB_PA0_CFG0
UART_MASTER_rx__0__PA__CFG1 EQU CYREG_UDB_PA0_CFG1
UART_MASTER_rx__0__PA__CFG10 EQU CYREG_UDB_PA0_CFG10
UART_MASTER_rx__0__PA__CFG11 EQU CYREG_UDB_PA0_CFG11
UART_MASTER_rx__0__PA__CFG12 EQU CYREG_UDB_PA0_CFG12
UART_MASTER_rx__0__PA__CFG13 EQU CYREG_UDB_PA0_CFG13
UART_MASTER_rx__0__PA__CFG14 EQU CYREG_UDB_PA0_CFG14
UART_MASTER_rx__0__PA__CFG2 EQU CYREG_UDB_PA0_CFG2
UART_MASTER_rx__0__PA__CFG3 EQU CYREG_UDB_PA0_CFG3
UART_MASTER_rx__0__PA__CFG4 EQU CYREG_UDB_PA0_CFG4
UART_MASTER_rx__0__PA__CFG5 EQU CYREG_UDB_PA0_CFG5
UART_MASTER_rx__0__PA__CFG6 EQU CYREG_UDB_PA0_CFG6
UART_MASTER_rx__0__PA__CFG7 EQU CYREG_UDB_PA0_CFG7
UART_MASTER_rx__0__PA__CFG8 EQU CYREG_UDB_PA0_CFG8
UART_MASTER_rx__0__PA__CFG9 EQU CYREG_UDB_PA0_CFG9
UART_MASTER_rx__0__PC EQU CYREG_PRT0_PC
UART_MASTER_rx__0__PC2 EQU CYREG_PRT0_PC2
UART_MASTER_rx__0__PORT EQU 0
UART_MASTER_rx__0__PS EQU CYREG_PRT0_PS
UART_MASTER_rx__0__SHIFT EQU 4
UART_MASTER_rx__DR EQU CYREG_PRT0_DR
UART_MASTER_rx__INTCFG EQU CYREG_PRT0_INTCFG
UART_MASTER_rx__INTSTAT EQU CYREG_PRT0_INTSTAT
UART_MASTER_rx__MASK EQU 0x10
UART_MASTER_rx__PA__CFG0 EQU CYREG_UDB_PA0_CFG0
UART_MASTER_rx__PA__CFG1 EQU CYREG_UDB_PA0_CFG1
UART_MASTER_rx__PA__CFG10 EQU CYREG_UDB_PA0_CFG10
UART_MASTER_rx__PA__CFG11 EQU CYREG_UDB_PA0_CFG11
UART_MASTER_rx__PA__CFG12 EQU CYREG_UDB_PA0_CFG12
UART_MASTER_rx__PA__CFG13 EQU CYREG_UDB_PA0_CFG13
UART_MASTER_rx__PA__CFG14 EQU CYREG_UDB_PA0_CFG14
UART_MASTER_rx__PA__CFG2 EQU CYREG_UDB_PA0_CFG2
UART_MASTER_rx__PA__CFG3 EQU CYREG_UDB_PA0_CFG3
UART_MASTER_rx__PA__CFG4 EQU CYREG_UDB_PA0_CFG4
UART_MASTER_rx__PA__CFG5 EQU CYREG_UDB_PA0_CFG5
UART_MASTER_rx__PA__CFG6 EQU CYREG_UDB_PA0_CFG6
UART_MASTER_rx__PA__CFG7 EQU CYREG_UDB_PA0_CFG7
UART_MASTER_rx__PA__CFG8 EQU CYREG_UDB_PA0_CFG8
UART_MASTER_rx__PA__CFG9 EQU CYREG_UDB_PA0_CFG9
UART_MASTER_rx__PC EQU CYREG_PRT0_PC
UART_MASTER_rx__PC2 EQU CYREG_PRT0_PC2
UART_MASTER_rx__PORT EQU 0
UART_MASTER_rx__PS EQU CYREG_PRT0_PS
UART_MASTER_rx__SHIFT EQU 4
UART_MASTER_SCB__BIST_CONTROL EQU CYREG_SCB1_BIST_CONTROL
UART_MASTER_SCB__BIST_DATA EQU CYREG_SCB1_BIST_DATA
UART_MASTER_SCB__CTRL EQU CYREG_SCB1_CTRL
UART_MASTER_SCB__EZ_DATA00 EQU CYREG_SCB1_EZ_DATA00
UART_MASTER_SCB__EZ_DATA01 EQU CYREG_SCB1_EZ_DATA01
UART_MASTER_SCB__EZ_DATA02 EQU CYREG_SCB1_EZ_DATA02
UART_MASTER_SCB__EZ_DATA03 EQU CYREG_SCB1_EZ_DATA03
UART_MASTER_SCB__EZ_DATA04 EQU CYREG_SCB1_EZ_DATA04
UART_MASTER_SCB__EZ_DATA05 EQU CYREG_SCB1_EZ_DATA05
UART_MASTER_SCB__EZ_DATA06 EQU CYREG_SCB1_EZ_DATA06
UART_MASTER_SCB__EZ_DATA07 EQU CYREG_SCB1_EZ_DATA07
UART_MASTER_SCB__EZ_DATA08 EQU CYREG_SCB1_EZ_DATA08
UART_MASTER_SCB__EZ_DATA09 EQU CYREG_SCB1_EZ_DATA09
UART_MASTER_SCB__EZ_DATA10 EQU CYREG_SCB1_EZ_DATA10
UART_MASTER_SCB__EZ_DATA11 EQU CYREG_SCB1_EZ_DATA11
UART_MASTER_SCB__EZ_DATA12 EQU CYREG_SCB1_EZ_DATA12
UART_MASTER_SCB__EZ_DATA13 EQU CYREG_SCB1_EZ_DATA13
UART_MASTER_SCB__EZ_DATA14 EQU CYREG_SCB1_EZ_DATA14
UART_MASTER_SCB__EZ_DATA15 EQU CYREG_SCB1_EZ_DATA15
UART_MASTER_SCB__EZ_DATA16 EQU CYREG_SCB1_EZ_DATA16
UART_MASTER_SCB__EZ_DATA17 EQU CYREG_SCB1_EZ_DATA17
UART_MASTER_SCB__EZ_DATA18 EQU CYREG_SCB1_EZ_DATA18
UART_MASTER_SCB__EZ_DATA19 EQU CYREG_SCB1_EZ_DATA19
UART_MASTER_SCB__EZ_DATA20 EQU CYREG_SCB1_EZ_DATA20
UART_MASTER_SCB__EZ_DATA21 EQU CYREG_SCB1_EZ_DATA21
UART_MASTER_SCB__EZ_DATA22 EQU CYREG_SCB1_EZ_DATA22
UART_MASTER_SCB__EZ_DATA23 EQU CYREG_SCB1_EZ_DATA23
UART_MASTER_SCB__EZ_DATA24 EQU CYREG_SCB1_EZ_DATA24
UART_MASTER_SCB__EZ_DATA25 EQU CYREG_SCB1_EZ_DATA25
UART_MASTER_SCB__EZ_DATA26 EQU CYREG_SCB1_EZ_DATA26
UART_MASTER_SCB__EZ_DATA27 EQU CYREG_SCB1_EZ_DATA27
UART_MASTER_SCB__EZ_DATA28 EQU CYREG_SCB1_EZ_DATA28
UART_MASTER_SCB__EZ_DATA29 EQU CYREG_SCB1_EZ_DATA29
UART_MASTER_SCB__EZ_DATA30 EQU CYREG_SCB1_EZ_DATA30
UART_MASTER_SCB__EZ_DATA31 EQU CYREG_SCB1_EZ_DATA31
UART_MASTER_SCB__I2C_CFG EQU CYREG_SCB1_I2C_CFG
UART_MASTER_SCB__I2C_CTRL EQU CYREG_SCB1_I2C_CTRL
UART_MASTER_SCB__I2C_M_CMD EQU CYREG_SCB1_I2C_M_CMD
UART_MASTER_SCB__I2C_S_CMD EQU CYREG_SCB1_I2C_S_CMD
UART_MASTER_SCB__I2C_STATUS EQU CYREG_SCB1_I2C_STATUS
UART_MASTER_SCB__INTR_CAUSE EQU CYREG_SCB1_INTR_CAUSE
UART_MASTER_SCB__INTR_I2C_EC EQU CYREG_SCB1_INTR_I2C_EC
UART_MASTER_SCB__INTR_I2C_EC_MASK EQU CYREG_SCB1_INTR_I2C_EC_MASK
UART_MASTER_SCB__INTR_I2C_EC_MASKED EQU CYREG_SCB1_INTR_I2C_EC_MASKED
UART_MASTER_SCB__INTR_M EQU CYREG_SCB1_INTR_M
UART_MASTER_SCB__INTR_M_MASK EQU CYREG_SCB1_INTR_M_MASK
UART_MASTER_SCB__INTR_M_MASKED EQU CYREG_SCB1_INTR_M_MASKED
UART_MASTER_SCB__INTR_M_SET EQU CYREG_SCB1_INTR_M_SET
UART_MASTER_SCB__INTR_RX EQU CYREG_SCB1_INTR_RX
UART_MASTER_SCB__INTR_RX_MASK EQU CYREG_SCB1_INTR_RX_MASK
UART_MASTER_SCB__INTR_RX_MASKED EQU CYREG_SCB1_INTR_RX_MASKED
UART_MASTER_SCB__INTR_RX_SET EQU CYREG_SCB1_INTR_RX_SET
UART_MASTER_SCB__INTR_S EQU CYREG_SCB1_INTR_S
UART_MASTER_SCB__INTR_S_MASK EQU CYREG_SCB1_INTR_S_MASK
UART_MASTER_SCB__INTR_S_MASKED EQU CYREG_SCB1_INTR_S_MASKED
UART_MASTER_SCB__INTR_S_SET EQU CYREG_SCB1_INTR_S_SET
UART_MASTER_SCB__INTR_SPI_EC EQU CYREG_SCB1_INTR_SPI_EC
UART_MASTER_SCB__INTR_SPI_EC_MASK EQU CYREG_SCB1_INTR_SPI_EC_MASK
UART_MASTER_SCB__INTR_SPI_EC_MASKED EQU CYREG_SCB1_INTR_SPI_EC_MASKED
UART_MASTER_SCB__INTR_TX EQU CYREG_SCB1_INTR_TX
UART_MASTER_SCB__INTR_TX_MASK EQU CYREG_SCB1_INTR_TX_MASK
UART_MASTER_SCB__INTR_TX_MASKED EQU CYREG_SCB1_INTR_TX_MASKED
UART_MASTER_SCB__INTR_TX_SET EQU CYREG_SCB1_INTR_TX_SET
UART_MASTER_SCB__RX_CTRL EQU CYREG_SCB1_RX_CTRL
UART_MASTER_SCB__RX_FIFO_CTRL EQU CYREG_SCB1_RX_FIFO_CTRL
UART_MASTER_SCB__RX_FIFO_RD EQU CYREG_SCB1_RX_FIFO_RD
UART_MASTER_SCB__RX_FIFO_RD_SILENT EQU CYREG_SCB1_RX_FIFO_RD_SILENT
UART_MASTER_SCB__RX_FIFO_STATUS EQU CYREG_SCB1_RX_FIFO_STATUS
UART_MASTER_SCB__RX_MATCH EQU CYREG_SCB1_RX_MATCH
UART_MASTER_SCB__SPI_CTRL EQU CYREG_SCB1_SPI_CTRL
UART_MASTER_SCB__SPI_STATUS EQU CYREG_SCB1_SPI_STATUS
UART_MASTER_SCB__SS0_POSISTION EQU 0
UART_MASTER_SCB__SS1_POSISTION EQU 1
UART_MASTER_SCB__SS2_POSISTION EQU 2
UART_MASTER_SCB__SS3_POSISTION EQU 3
UART_MASTER_SCB__STATUS EQU CYREG_SCB1_STATUS
UART_MASTER_SCB__TX_CTRL EQU CYREG_SCB1_TX_CTRL
UART_MASTER_SCB__TX_FIFO_CTRL EQU CYREG_SCB1_TX_FIFO_CTRL
UART_MASTER_SCB__TX_FIFO_STATUS EQU CYREG_SCB1_TX_FIFO_STATUS
UART_MASTER_SCB__TX_FIFO_WR EQU CYREG_SCB1_TX_FIFO_WR
UART_MASTER_SCB__UART_CTRL EQU CYREG_SCB1_UART_CTRL
UART_MASTER_SCB__UART_RX_CTRL EQU CYREG_SCB1_UART_RX_CTRL
UART_MASTER_SCB__UART_RX_STATUS EQU CYREG_SCB1_UART_RX_STATUS
UART_MASTER_SCB__UART_TX_CTRL EQU CYREG_SCB1_UART_TX_CTRL
UART_MASTER_SCB_IRQ__INTC_CLR_EN_REG EQU CYREG_CM0_ICER
UART_MASTER_SCB_IRQ__INTC_CLR_PD_REG EQU CYREG_CM0_ICPR
UART_MASTER_SCB_IRQ__INTC_MASK EQU 0x800
UART_MASTER_SCB_IRQ__INTC_NUMBER EQU 11
UART_MASTER_SCB_IRQ__INTC_PRIOR_MASK EQU 0xC0000000
UART_MASTER_SCB_IRQ__INTC_PRIOR_NUM EQU 3
UART_MASTER_SCB_IRQ__INTC_PRIOR_REG EQU CYREG_CM0_IPR2
UART_MASTER_SCB_IRQ__INTC_SET_EN_REG EQU CYREG_CM0_ISER
UART_MASTER_SCB_IRQ__INTC_SET_PD_REG EQU CYREG_CM0_ISPR
UART_MASTER_SCBCLK__DIVIDER_MASK EQU 0x0000FFFF
UART_MASTER_SCBCLK__ENABLE EQU CYREG_CLK_DIVIDER_A00
UART_MASTER_SCBCLK__ENABLE_MASK EQU 0x80000000
UART_MASTER_SCBCLK__MASK EQU 0x80000000
UART_MASTER_SCBCLK__REGISTER EQU CYREG_CLK_DIVIDER_A00
UART_MASTER_tx__0__DM__MASK EQU 0x38000
UART_MASTER_tx__0__DM__SHIFT EQU 15
UART_MASTER_tx__0__DR EQU CYREG_PRT0_DR
UART_MASTER_tx__0__HSIOM EQU CYREG_HSIOM_PORT_SEL0
UART_MASTER_tx__0__HSIOM_GPIO EQU 0
UART_MASTER_tx__0__HSIOM_I2C EQU 14
UART_MASTER_tx__0__HSIOM_I2C_SDA EQU 14
UART_MASTER_tx__0__HSIOM_MASK EQU 0x00F00000
UART_MASTER_tx__0__HSIOM_SHIFT EQU 20
UART_MASTER_tx__0__HSIOM_SPI EQU 15
UART_MASTER_tx__0__HSIOM_SPI_MISO EQU 15
UART_MASTER_tx__0__HSIOM_UART EQU 9
UART_MASTER_tx__0__HSIOM_UART_TX EQU 9
UART_MASTER_tx__0__INTCFG EQU CYREG_PRT0_INTCFG
UART_MASTER_tx__0__INTSTAT EQU CYREG_PRT0_INTSTAT
UART_MASTER_tx__0__MASK EQU 0x20
UART_MASTER_tx__0__OUT_SEL EQU CYREG_UDB_PA0_CFG10
UART_MASTER_tx__0__OUT_SEL_SHIFT EQU 10
UART_MASTER_tx__0__OUT_SEL_VAL EQU -1
UART_MASTER_tx__0__PA__CFG0 EQU CYREG_UDB_PA0_CFG0
UART_MASTER_tx__0__PA__CFG1 EQU CYREG_UDB_PA0_CFG1
UART_MASTER_tx__0__PA__CFG10 EQU CYREG_UDB_PA0_CFG10
UART_MASTER_tx__0__PA__CFG11 EQU CYREG_UDB_PA0_CFG11
UART_MASTER_tx__0__PA__CFG12 EQU CYREG_UDB_PA0_CFG12
UART_MASTER_tx__0__PA__CFG13 EQU CYREG_UDB_PA0_CFG13
UART_MASTER_tx__0__PA__CFG14 EQU CYREG_UDB_PA0_CFG14
UART_MASTER_tx__0__PA__CFG2 EQU CYREG_UDB_PA0_CFG2
UART_MASTER_tx__0__PA__CFG3 EQU CYREG_UDB_PA0_CFG3
UART_MASTER_tx__0__PA__CFG4 EQU CYREG_UDB_PA0_CFG4
UART_MASTER_tx__0__PA__CFG5 EQU CYREG_UDB_PA0_CFG5
UART_MASTER_tx__0__PA__CFG6 EQU CYREG_UDB_PA0_CFG6
UART_MASTER_tx__0__PA__CFG7 EQU CYREG_UDB_PA0_CFG7
UART_MASTER_tx__0__PA__CFG8 EQU CYREG_UDB_PA0_CFG8
UART_MASTER_tx__0__PA__CFG9 EQU CYREG_UDB_PA0_CFG9
UART_MASTER_tx__0__PC EQU CYREG_PRT0_PC
UART_MASTER_tx__0__PC2 EQU CYREG_PRT0_PC2
UART_MASTER_tx__0__PORT EQU 0
UART_MASTER_tx__0__PS EQU CYREG_PRT0_PS
UART_MASTER_tx__0__SHIFT EQU 5
UART_MASTER_tx__DR EQU CYREG_PRT0_DR
UART_MASTER_tx__INTCFG EQU CYREG_PRT0_INTCFG
UART_MASTER_tx__INTSTAT EQU CYREG_PRT0_INTSTAT
UART_MASTER_tx__MASK EQU 0x20
UART_MASTER_tx__PA__CFG0 EQU CYREG_UDB_PA0_CFG0
UART_MASTER_tx__PA__CFG1 EQU CYREG_UDB_PA0_CFG1
UART_MASTER_tx__PA__CFG10 EQU CYREG_UDB_PA0_CFG10
UART_MASTER_tx__PA__CFG11 EQU CYREG_UDB_PA0_CFG11
UART_MASTER_tx__PA__CFG12 EQU CYREG_UDB_PA0_CFG12
UART_MASTER_tx__PA__CFG13 EQU CYREG_UDB_PA0_CFG13
UART_MASTER_tx__PA__CFG14 EQU CYREG_UDB_PA0_CFG14
UART_MASTER_tx__PA__CFG2 EQU CYREG_UDB_PA0_CFG2
UART_MASTER_tx__PA__CFG3 EQU CYREG_UDB_PA0_CFG3
UART_MASTER_tx__PA__CFG4 EQU CYREG_UDB_PA0_CFG4
UART_MASTER_tx__PA__CFG5 EQU CYREG_UDB_PA0_CFG5
UART_MASTER_tx__PA__CFG6 EQU CYREG_UDB_PA0_CFG6
UART_MASTER_tx__PA__CFG7 EQU CYREG_UDB_PA0_CFG7
UART_MASTER_tx__PA__CFG8 EQU CYREG_UDB_PA0_CFG8
UART_MASTER_tx__PA__CFG9 EQU CYREG_UDB_PA0_CFG9
UART_MASTER_tx__PC EQU CYREG_PRT0_PC
UART_MASTER_tx__PC2 EQU CYREG_PRT0_PC2
UART_MASTER_tx__PORT EQU 0
UART_MASTER_tx__PS EQU CYREG_PRT0_PS
UART_MASTER_tx__SHIFT EQU 5

/* Miscellaneous */
CYDEV_BCLK__HFCLK__HZ EQU 24000000
CYDEV_BCLK__HFCLK__KHZ EQU 24000
CYDEV_BCLK__HFCLK__MHZ EQU 24
CYDEV_BCLK__SYSCLK__HZ EQU 24000000
CYDEV_BCLK__SYSCLK__KHZ EQU 24000
CYDEV_BCLK__SYSCLK__MHZ EQU 24
CYDEV_CHIP_DIE_LEOPARD EQU 1
CYDEV_CHIP_DIE_PSOC4A EQU 18
CYDEV_CHIP_DIE_PSOC5LP EQU 2
CYDEV_CHIP_DIE_PSOC5TM EQU 3
CYDEV_CHIP_DIE_TMA4 EQU 4
CYDEV_CHIP_DIE_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_FM0P EQU 5
CYDEV_CHIP_FAMILY_FM3 EQU 6
CYDEV_CHIP_FAMILY_FM4 EQU 7
CYDEV_CHIP_FAMILY_PSOC3 EQU 1
CYDEV_CHIP_FAMILY_PSOC4 EQU 2
CYDEV_CHIP_FAMILY_PSOC5 EQU 3
CYDEV_CHIP_FAMILY_PSOC6 EQU 4
CYDEV_CHIP_FAMILY_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC4
CYDEV_CHIP_JTAG_ID EQU 0x04C81193
CYDEV_CHIP_MEMBER_3A EQU 1
CYDEV_CHIP_MEMBER_4A EQU 18
CYDEV_CHIP_MEMBER_4D EQU 13
CYDEV_CHIP_MEMBER_4E EQU 6
CYDEV_CHIP_MEMBER_4F EQU 19
CYDEV_CHIP_MEMBER_4G EQU 4
CYDEV_CHIP_MEMBER_4H EQU 17
CYDEV_CHIP_MEMBER_4I EQU 23
CYDEV_CHIP_MEMBER_4J EQU 14
CYDEV_CHIP_MEMBER_4K EQU 15
CYDEV_CHIP_MEMBER_4L EQU 22
CYDEV_CHIP_MEMBER_4M EQU 21
CYDEV_CHIP_MEMBER_4N EQU 10
CYDEV_CHIP_MEMBER_4O EQU 7
CYDEV_CHIP_MEMBER_4P EQU 20
CYDEV_CHIP_MEMBER_4Q EQU 12
CYDEV_CHIP_MEMBER_4R EQU 8
CYDEV_CHIP_MEMBER_4S EQU 11
CYDEV_CHIP_MEMBER_4T EQU 9
CYDEV_CHIP_MEMBER_4U EQU 5
CYDEV_CHIP_MEMBER_4V EQU 16
CYDEV_CHIP_MEMBER_5A EQU 3
CYDEV_CHIP_MEMBER_5B EQU 2
CYDEV_CHIP_MEMBER_6A EQU 24
CYDEV_CHIP_MEMBER_FM3 EQU 28
CYDEV_CHIP_MEMBER_FM4 EQU 29
CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 25
CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 26
CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 27
CYDEV_CHIP_MEMBER_UNKNOWN EQU 0
CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_4A
CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED
CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3
CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17
CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
CYDEV_CHIP_REV_PSOC5TM_ES0 EQU 0
CYDEV_CHIP_REV_PSOC5TM_ES1 EQU 1
CYDEV_CHIP_REV_PSOC5TM_PRODUCTION EQU 1
CYDEV_CHIP_REV_TMA4_ES EQU 17
CYDEV_CHIP_REV_TMA4_ES2 EQU 33
CYDEV_CHIP_REV_TMA4_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_3A_ES1 EQU 0
CYDEV_CHIP_REVISION_3A_ES2 EQU 1
CYDEV_CHIP_REVISION_3A_ES3 EQU 3
CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3
CYDEV_CHIP_REVISION_4A_ES0 EQU 17
CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD EQU 0
CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA EQU 0
CYDEV_CHIP_REVISION_4F_PRODUCTION_256K EQU 0
CYDEV_CHIP_REVISION_4G_ES EQU 17
CYDEV_CHIP_REVISION_4G_ES2 EQU 33
CYDEV_CHIP_REVISION_4G_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_4H_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4I_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4J_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4K_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4L_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4M_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4N_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4O_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4P_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4Q_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4R_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4S_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4T_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4V_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_5A_ES0 EQU 0
CYDEV_CHIP_REVISION_5A_ES1 EQU 1
CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1
CYDEV_CHIP_REVISION_5B_ES0 EQU 0
CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_6A_ES EQU 17
CYDEV_CHIP_REVISION_6A_NO_UDB EQU 33
CYDEV_CHIP_REVISION_6A_PRODUCTION EQU 33
CYDEV_CHIP_REVISION_FM3_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_4A_PRODUCTION
CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED
CYDEV_CONFIG_READ_ACCELERATOR EQU 1
CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0
CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_Disallowed
CYDEV_CONFIGURATION_COMPRESSED EQU 1
CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED
CYDEV_CONFIGURATION_MODE_DMA EQU 2
CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1
CYDEV_DEBUG_PROTECT_KILL EQU 4
CYDEV_DEBUG_PROTECT_OPEN EQU 1
CYDEV_DEBUG_PROTECT EQU CYDEV_DEBUG_PROTECT_OPEN
CYDEV_DEBUG_PROTECT_PROTECTED EQU 2
CYDEV_DEBUGGING_DPS_Disable EQU 3
CYDEV_DEBUGGING_DPS_SWD EQU 2
CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD
CYDEV_DEBUGGING_ENABLE EQU 1
CYDEV_DFT_SELECT_CLK0 EQU 1
CYDEV_DFT_SELECT_CLK1 EQU 2
CYDEV_HEAP_SIZE EQU 0x80
CYDEV_IMO_TRIMMED_BY_USB EQU 0
CYDEV_IMO_TRIMMED_BY_WCO EQU 0
CYDEV_IS_EXPORTING_CODE EQU 0
CYDEV_IS_IMPORTING_CODE EQU 0
CYDEV_PROJ_TYPE EQU 0
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1
CYDEV_PROJ_TYPE_LAUNCHER EQU 5
CYDEV_PROJ_TYPE_LOADABLE EQU 2
CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER EQU 4
CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3
CYDEV_PROJ_TYPE_STANDARD EQU 0
CYDEV_STACK_SIZE EQU 0x0400
CYDEV_USE_BUNDLED_CMSIS EQU 1
CYDEV_VARIABLE_VDDA EQU 1
CYDEV_VDDA_MV EQU 3300
CYDEV_VDDD_MV EQU 3300
CYDEV_WDT_GENERATE_ISR EQU 1
CYIPBLOCK_M0S8_CTBM_VERSION EQU 0
CYIPBLOCK_m0s8cpuss_VERSION EQU 0
CYIPBLOCK_m0s8csd_VERSION EQU 0
CYIPBLOCK_m0s8gpio2_VERSION EQU 0
CYIPBLOCK_m0s8hsiom4a_VERSION EQU 0
CYIPBLOCK_m0s8lcd_VERSION EQU 0
CYIPBLOCK_m0s8lpcomp_VERSION EQU 0
CYIPBLOCK_m0s8pclk_VERSION EQU 0
CYIPBLOCK_m0s8sar_VERSION EQU 0
CYIPBLOCK_m0s8scb_VERSION EQU 0
CYIPBLOCK_m0s8srssv2_VERSION EQU 1
CYIPBLOCK_m0s8tcpwm_VERSION EQU 0
CYIPBLOCK_m0s8udbif_VERSION EQU 0
CYIPBLOCK_S8_GPIO_VERSION EQU 2
CYDEV_BOOTLOADER_ENABLE EQU 0

#endif /* INCLUDED_CYFITTERIAR_INC */
